In general, when all the memory cells of an electrically erasable and programmable non-volatile semiconductor memory device are collectively erased data of "0" are written into them in advance in order to equalize their threshold levels. Then, a high voltage is applied to a memory cell source wire, which is connected with the respective memory cell sources, in order to erase the data stored in them. Subsequently, the application of high voltage to the memory cell source wire is stopped, and whether all the memory cells are erased or not is discriminated, which is called "erase verify". When the operation of the memory device shift's from a high voltage application to erase verify, the memory cell is connected with the ground plane via a switching transistor with high current driving capability in most cases. However, the potential of the memory cell source wire sinks under the ground potential for a short time after the switching transistor turns on. Consequently, the potential of the word wires, which are capacitively coupled with the memory cell source wire sinks under the ground potential also. Since the word wires are respectively connected with the gates of the cell transistors, the step of erase very becomes unstable. The aforementioned high voltage is applied to the memory cell source wire in the form of pulse, and the non-volatile semiconductor device is provided with a memory cell erasing circuit in usual.